Multiplexing pixel circuits

ABSTRACT

An active matrix display in accordance with the present invention includes a plurality of pixels arranged in an array. At least two transistors associated with each pixel are included. The transistors are serially connected to each other and disposed within the array for switching the pixels on and off according to data and gate signals. A data line is coupled to a first end of the serially connected transistors for each pixel. A second end of the serially connected transistors is coupled to a storage device. The serially connected transistors provide multiplexing capability for at least one of data signal multiplexing and gate signal multiplexing.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to pixel display circuits and, moreparticularly, to a circuit for providing integrated data and gatemultiplexing without impact to acceptable standards for displays.

2. Description of the Related Art

Due to poor charging ability in amorphous silicon thin film transistors(a-Si TFTs) resulting from inherently low TFT transconductance, allcommercially available a-Si TFT liquid crystal displays (LCD) include anarray of pixel elements connected with row and column metal lines. Therow and column drivers require higher transconductance devices. The rowand column drivers typically include crystalline silicon technology andare separately fabricated and attached to the a-Si TFT LCDs. Over theyears, there have been attempts at integrating some level ofmultiplexing between the attached crystalline silicon drivers and thepixel array. See for example, U.S. Pat. No. 5,175,446 to R. Stewart. Inthis way, the number of crystalline drivers needed could be reduced.These prior art designs follow a circuit approach that is commonly usedin crystalline silicon circuit designs. Even simple 2:1 levelmultiplexing schemes at the edge of a pixel array have not beenimplemented for a-Si TFT LCD circuits. Although not realized for directview a-Si TFT LCDs, multiplexer circuits have been implemented with somesuccess in smaller displays for example, in light valves and inpoly-silicon technology. Poly-silicon TFTs make it possible to realize ahigher transconductance TFT. However, implementing poly-silicontechnology on larger and/or high resolution TFT LCDs leads to anunacceptably higher RC load and/or higher bandwidth rates of the rowsand columns.

Therefore, a need exists for a circuit for providing integrated data andgate multiplexing for active matrix LCDs without impacting acceptabledisplay limits. A further need exists for a reduction in data driversand gate drivers to reduce costs of these displays.

SUMMARY OF THE INVENTION

An active matrix display in accordance with the present inventionincludes a plurality of pixels arranged in an array. At least twotransistors associated with each pixel are included. The transistors areserially connected to each other and disposed within the array forswitching the pixels on and off according to data and gate signals. Adata line is coupled to a first end of the serially connectedtransistors for each pixel. A second end of the serially connectedtransistors is coupled to a storage device. The serially connectedtransistors provide multiplexing capability for at least one of datasignal multiplexing and gate signal multiplexing.

Another active matrix display in accordance with the present inventionincludes a plurality of pixels arranged in an array including rows andcolumns. At least two transistors associated with each pixel, thetransistors being serially connected and positioned within the array forswitching the pixels on and off. A plurality of data lines runsubstantially parallel to the columns. A plurality of scan lines runsubstantially parallel to the rows. The data lines and scan lines beingcoupled to the transistors of the pixels such that the data linesprovide data multiplexing for each pixel and the scan lines provide gatemultiplexing for each pixel.

In alternate embodiments of the displays in accordance with theinvention, one of the at least two transistors may be shared betweenadjacent pixels to further reduce gate or data drivers. The pixels maymodulate light in a transmissive mode and/or a reflective mode. Thearray preferably includes rows and columns and the control lines mayselect the pixels in different rows simultaneously. The simultaneouslyselected pixels may share a data line. Control lines may include datalines and the simultaneously selected pixels may each use a differentdata line. The control lines may includes scan lines and/or capacitancestorage lines. The control lines may be coupled to the transistors by alow impedance contact path which may include a metal, polycrystallinesilicon, a capacitor or a combination thereof. The display may include aliquid crystal display, and the transistors preferably include thin filmtransistors.

The data multiplexing may include L:1 multiplexing where L is an integergreater than one. The gate multiplexing may include m:1 multiplexingwhere m is an integer greater than one. The data lines may select pixelsin different rows simultaneously, or the pixels may share a data line.The display may further include logic circuitry for controlling themultiplexing in accordance with control signals. The transistors arepreferably disposed on a substrate and the pixels are formed over thetransistors

These and other objects, features and advantages of the presentinvention will become apparent from the following detailed descriptionof illustrative embodiments thereof, which is to be read in connectionwith the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

The invention will be described in detail in the following descriptionof preferred embodiments with reference to the following figureswherein:

FIG. 1 is a schematic diagram of a pixel circuit showing two TFTs inseries per pixel in accordance with the present invention;

FIG. 2 is a timing diagram for the circuit of FIG. 1 in accordance withthe present invention;

FIG. 3 is a schematic diagram of a pixel circuit showing three TFTs inseries per pixel and additional scan lines in accordance with thepresent invention;

FIG. 4 is a timing diagram for the circuit of FIG. 3 in accordance withthe present invention;

FIG. 5 is a schematic diagram of another pixel circuit showing two TFTsin series per pixel in accordance with the present invention;

FIG. 6 is a timing diagram for the circuit of FIG. 5 in accordance withthe present invention;

FIG. 7 is a schematic diagram of a pixel circuit effectively having oneand one half TFTs per pixel due to a shared TFT between adjacent pixelsin accordance with the present invention;

FIG. 8 is a timing diagram for the circuit of FIG. 7 in accordance withthe present invention;

FIG. 9 is a schematic diagram showing a fanout wiring for ademultiplexer in an active matrix array in accordance with the presentinvention;

FIG. 10 is a schematic diagram of another embodiment of the pixelcircuit of FIG. 5 showing an additional scan line to achieve 4:1multiplexing in accordance with the present invention;

FIG. 11 is a timing diagram for the circuit of FIG. 10 in accordancewith the present invention;

FIG. 12 is a schematic diagram of a pixel circuit having a four pixellayout with a common data line and three TFTs in series per pixel inaccordance with the present invention;

FIG. 13 is a timing diagram for the circuit of FIG. 12 in accordancewith the present invention;

FIG. 14 is a schematic diagram of a pixel circuit effectively having oneand one half TFTs per pixel due to a shared TFT between adjacent pixelsfor 4:1 multiplexing in accordance with the present invention;

FIG. 15 is a timing diagram for the circuit of FIG. 14 in accordancewith the present invention; and

FIG. 16 is a top plan view of a semiconductor device layout implementingthe present invention and showing logic circuitry.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention relates to liquid crystal display circuits and,more particularly, to a circuit for providing integrated data and gatemultiplexing without impact to acceptable standards of the displays. Thepresent invention provides a novel design for introducing gate and dataline multiplexing functions from circuitry implemented within the pixelrather than from circuitry at the data or gate line ends. The presentinvention does not follow the prior art schemes of implementingcrystalline silicon multiplexer designs with amorphous silicon thin filmtransistors (TFTs), nor does the present invention follow the prior artscheme of placing the multiplexers between the pixel array and theexternally attached crystalline silicon drivers.

The present invention provides an RC load that is reduced to about aload within a pixel. This may be implemented by employing a TFT gate ofminimum length and width as described hereinbelow. Whereas the prior artneeded to drive a full load of the gate or data line to accomplish gateor data multiplexing.

The present invention employs more than one TFT in a pixel. All TFTswithin the pixel are connected in series. This connection includes afirst source connected to a data line and a last drain in the series ofTFTs connected to a storage capacitor and/or an LC capacitor.Multiplexing as provided by the present invention places the multiplexercircuitry within each pixel and employs several serially connected TFTsto provide the multiplexing function. A data line is connected to thesource of one TFT, and the drain of this TFT is connected to the sourceof another TFT and so on until the last serially connected TFT has itsdrain connected to one electrode of a storage capacitor and a liquidcrystal flag. The liquid crystal flag (not shown) is one of theelectrodes forming a liquid crystal capacitor. The liquid crystal flagis preferably formed from indium-tin oxide (ITO).

The number of serially connected TFTs may be two or more. The more TFTsper pixel, the higher the level of multiplexing that may by implemented.However, the more TFTs per pixel the lower the aperture ratio for thatpixel since the amount of available chip area is reduced by the presenceof the TFTs and enable lines connected thereto. There is no minimumaperture ratio for reflective displays since the circuitry may be placedbelow reflector pixels. Referring now in detail to the figures in whichlike numerals represent the same or similar elements and initially toFIG. 1, a schematic diagram of a two pixel circuit 10 in accordance withthe present invention is shown. Pixel circuit 10 includes two pixels 12with a common data line (DATA LINE) and two thin film transistors(TFTs)per pixel 12, M2 and M3 and M5 and M6, respectively. Enabling TFTsM2 and M5 are activated by scan line B and scan line E, respectively.Data line signal transfer TFTs M3 and M6 provide access from DATA LINEto pixel capacitors CLC1 and CLC2. M3 and M6 are enabled by scan line Aand scan line F, respectively. Advantageously, all TFTs shown in FIG. 1are located at pixels 12. An illustrative timing diagram is shown inFIG. 2 to show the states of pixel circuit 10 of FIG. 1.

Referring to FIG. 3, a schematic diagram shows an alternate embodimentof a pixel circuit shown as pixel circuit 20. Circuit 20 includesadditional enabling TFTs M1 and M4 in series with the other TFTs. TFTsM1 and M4 are enabled by signal line C and signal line D, respectively.In a similar way, additional enabling TFTs may be added in series withthe TFTS to provide a similar function. The additional TFTs in seriesprovide, among other things, a higher level of gate line multiplexing,more scan lines through each pixel 22 and an integer number of thresholddrops from scan line C (or D) voltage to a gate of TFT M3 (or M6). It isto be understood that if a data voltage at the source of a first TFT (M1or M4), connected to DATA LINE, is comparable to an ENABLE voltage, acumulative threshold voltage drop in the data voltage after each TFTwill result. This TFT threshold voltage alteration on the data voltagemay be rendered nonexistent if the pixel TFTs are overdriven such thatthe ENABLE voltage is at least one threshold voltage larger than themaximum data line voltage. In one example for amorphous silicon TFTLCDs, this condition is easily satisfied since the data voltage istypically in the range of 10 V or less (i.e., ±5 V centered around a topplate common voltage of about 7 V), and the “on” gate voltage (thatwould be comparable to the ENABLE voltage) is approximately 13 V orgreater than the maximum data voltage, or approximately 25 V. FIG. 4illustratively presents a timing diagram for circuit 20 of FIG. 3.

Referring to FIG. 5, another embodiment of the present invention isshown as pixel circuit 30. The number of scan lines are reduced toeffectively two per pixel. Scan lines between pixels are shared toreduce their number. As shown in circuit 30, scan line D is shared witha previous row of pixels where scan line C is shared with a next row ofpixels. Circuit 30 provides a more efficient layout of pixels and thusmaximizes aperture area.

An illustrative timing diagram is shown for circuit 30 in FIG. 6.Referring now to FIGS. 5 and 6, a mode of operation is provided wherescan line A pulse high width overlaps scan line C and scan line Dpulses. The significance of this is that the falling edge of scan line Apulses are completed after that of scan line C of scan line D fallingedges so as to ensure that a gate node of M3 or M6 is discharged andwill not act as a charge storage node which would prevent M3 and/or M6from turning off. Further, only two scan lines are needed to turn apixel on, for example, scan line A and D or scan line A and C. The thirdscan line provides a multiplexing capability in accordance with thepresent invention. In this example, a shared common DATA LINE betweenpixels 32 provides a 2:1 data multiplexing function, and the three scanlines A, C and D provide an m:1 gate demultiplexing function, where m isan integer greater than 1.

The pulse width on scan line A is larger than that on scan line C or D.This implementation provides scan line pulse flexibility and in general,scan line pulse widths and relative positions may be different betweenscan line A and scan line D and scan line C. For example, when scan lineA is high, enable TFTs M2 and MS are turned on. Scan line C and Dvoltages are placed on gates of TFTs M3 and M6, respectively. If scanline C (or D) is high, TFT M3 (or M6) conducts and transfers a datavoltage to storage capacitors CS1 (or CS2). If scan line C (or D) islow, TFT M3 (or M6) does not conduct, and the data line voltage is nottransferred to CS1 (or CS2). The timing diagram of FIG. 6 is for normalscan line multiplexing. For simplicity, a liquid crystal voltage is notshown, however the liquid crystal voltage is connected across a sourceof TFT M3 (M6) where CS1 (CS2) is connected and the other node isconnected to a common plate voltage. The common plate extends over asurface of the device and is preferably formed from ITO.

Referring to FIG. 7, a circuit 40 is shown which is another embodimentof circuit 30 of FIG. 5. In circuit 40, the serially accessed andredundant enable TFTs (M5 and M2) of circuit 30 are replaced with asingle TFT M2′ which is shared between two pixels. FIG. 8 illustrativelypresents a timing diagram for circuit 40 of FIG. 7.

Referring to FIG. 9, an illustrative example of row fan-out wiring forgate demultiplexing is shown. An m:1 gate multiplexing function isprovided. Signal line labeled “EN1 o/e” through EN m*n o/e” representpulses to the gates of the enable TFTs M2 and M5. The odd (M2) and even(M5) pixel access TFTs are designated by the nomenclature “o” and “e”.Also, “row #”1 through m*n represent scan lines to which the storagecapacitors (i.e., CS1 and CS2) overlap onto. In one example, if m=n, andXGA and SXGA color displays are used, gate driver outputs may bemultiplexed to approximately 28:1 and 32:1, respectively.

The above figures have shown gate driver outputs being multiplexed 2:1,however, higher data line multiplexing is possible through theintroduction of other scan lines.

Referring to FIG. 10, circuit 30 of FIG. 5 is shown as circuit 50 havingan additional scan line G to provide increased data multiplexing from2:1 to 4:1. Circuit 50 includes four pixels 52. The TFTs M8, M9, M11 andM12 function similarly to TFTs M2, M3, M5 and M6. CS3 and CS4 functionsimilarly to CS1 and CS2. By repeating the circuit pattern of FIG. 10, acircuit is provided in accordance with the present invention whichincorporates m:1 gate demultiplexing and L:1 data demultiplexing, wherem and L are integers greater than 1. FIG. 11 illustratively shows atiming diagram for circuit 50.

Referring to FIG. 12, a schematic diagram of a circuit 60 is shown.Circuit 60 includes a common DATA LINE and three TFTs per pixel 62.Circuit 60 is a 4:1 data demultiplexing representation of circuit 20 ofFIG. 3. Scan lines G, H, I and J are added to accomplish this. The TFTsare serially connected in groups of three (i.e., M1, M2, M3; M4, M5, M6;M7, M8, M9; and M10, M11, M12), each group functions similarly. CS1,CS2, CS3 and CS4 are storage capacitor nodes. FIG. 13 illustrates anexample of a timing diagram for circuit 60.

Referring to FIG. 14, a schematic diagram of a circuit 70 is shown.Circuit 70 includes a common DATA LINE and two TFTs per pixel 72 inwhich one TFT (M2, M8) is shared between two pixels (an efficient oneand one half (1½)TFT per pixel layout). Circuit 70 is a 4:1 datademultiplexing representation of circuit 40 of FIG. 7. Scan line G isadded to accomplish this. A common DATA LINE is used for four pixels 72.FIG. 15 illustrates an example of a timing diagram for circuit 70.

It is understood that the circuits described above may be implemented ona semiconductor device. Advantageously, circuit 30 yields a high aspectratio and provides a reduction in number of both data and gate driverswhen compared to the prior art X-Y addressed displays. Table 1 comparesthe number of lines needed for a display.

Table 1.

X=number of rows

Y=number of columns (i.e., RGB columns)

R_(xy)=Y/X information content aspect ratio of a panel (typically 4:3).

TABLE 1 total # total # of array of array connec- connec- # of # oftotal # tions for tions for Display horizontal vertical of array aspectaspect Address lines in lines in connec- ration ration Type array arraytions 4:3 16:9 Prior art   X 3Y or (1 + 3R_(xy))*X   5X ˜6.333X3R_(xy)*X Prior 1.5X 2Y or (1.5 + 2R_(xy))*X ˜4.167X ˜5.056X Art with2R_(xy)*X delta- RGB pixel layout Circuit   2X + 1 1.5Y or (2 +1.5R_(xy))*X   4X + 1 ˜4.667 + 40 1.5R_(xy)*X 1 X = number of rows Y =number of columns (i.e., RGB columns) R_(xy) = Y/X information contentaspect ratio of a panel (typically 4:3).

Table 1 illustratively demonstrates a reduction the present inventionyields for vertical lines. The result is a 2:1 data demultiplexingeffect. The total number of horizontal lines in the display may beincreased, however, if this is the case the total number of connections(lines for tabbing external drivers) for the 4:3 or the 16:9 aspectratio displays are minimized in accordance with the present invention.Further improvements in demultiplexing may be realized if the fanoutstructure as shown in FIG. 9 is employed. Gate drivers are furtherreduced in numbers and the data demultiplexing becomes m:1 where m is aninteger greater than one and equal to the number of stages implementedas described in FIG. 9.

Referring to FIG. 16, an illustrative layout is shown for animplementation of the present invention. Pixels 110 are shown. Betweenrows of pixels a circuit region 112 is provided in accordance with thepresent invention. Circuit region 112 may include TFTs, scan lines, datalines, storage node lines, connections, etc. as described. Alternately,circuit region 112 may include logic circuitry including AND gates orother logic gates such as OR, NOR, NAND and/or XOR gates. Thus, theselection of control lines such as scan lines will be performed usinglogic gates having control or enable signals which are logicallycombined to transmit an appropriate control signal to TFTs. Logic gatesmay also be included externally to the pixel areas.

Pixels 110 may include a transmissive mode and a reflective mode.Transmissive mode includes modulating light from a surface of pixel 110by modulating a capacitive voltage to the pixel to transmit lightdirectly therefrom. Reflective mode includes preparing the pixel tomodulate light therefrom by reflecting light incident on its surface.

It is to be understood that the present invention may be implementedwith various semiconductor technologies, for example crystallinesilicon, amorphous silicon, polysilicon, organic materials, Si—Ge and/orCdS. The embodiments of the present invention may be implemented on anyactive matrix display without impacting conventional fabricationprocesses. In preferred embodiments, the displays are used in lap topcomputers or other electronic devices having LCDs. Further, the presentinvention implements multiplexing/demultiplexing capability whilereducing components and cost. Layouts may have reduced area where thetransistors are disposed on a substrate and the pixels are formed overthe transistors in accordance with the invention.

Having described preferred embodiments of multiplexing pixel circuits(which are intended to be illustrative and not limiting), it is notedthat modifications and variations can be made by persons skilled in theart in light of the above teachings. It is therefore to be understoodthat changes may be made in the particular embodiments of the inventiondisclosed which are within the scope and spirit of the invention asoutlined by the appended claims. Having thus described the inventionwith the details and particularity required by the patent laws, what isclaimed and desired protected by Letters Patent is set forth in theappended claims.

What is claimed is:
 1. An active matrix display comprising: a pluralityof pixels arranged in an array, wherein the array comprises rows andcolumns and control lines select the pixels in different rowssimultaneously; at least two transistors associated with each pixel, thetransistors serially connected to each other and disposed within thearray for switching the pixels on and off according to data signals andgate signals; and a data line coupled to a first end of the seriallyconnected transistors and shared between the transistors of differentpixels; a second end of the serially connected transistors coupling to astorage device and the pixel; the serially connected transistorsproviding multiplexing for at least one data signal multiplexing andgate signal multiplexing of each pixel by selectively enabling the atleast two transistors for each pixel in accordance with the gatesignals.
 2. The display as recited in claim 1, wherein one of the atleast two transistors is shared between adjacent pixels.
 3. The displayas recited in claim 1, wherein the pixels modulate light in atransmissive mode.
 4. The display as recited in claim 1, wherein thepixels modulate light in a reflective mode.
 5. The display as recited inclaim 1, wherein the control lines include data lines and thesimultaneously selected pixels share a data line.
 6. The display asrecited in claim 1, wherein the control lines include data lines and thesimultaneously selected pixels each use a different data line.
 7. Thedisplay as recited in claim 1, further comprising scan lines forconnecting to gates of the transistors for activating the transistors.8. The display as recited in claim 7, wherein the scan lines includecapacitance storage lines.
 9. The display as recited in claim 1, whereincontrol lines are coupled to the transistors by a low impedance path.10. The display as recited in claim 9, wherein the low impedance pathincludes one of a metal, a doped amorphous silicon and a polycrystallinesilicon.
 11. The display as recited in claim 9, wherein the lowimpedance path includes a capacitor.
 12. The display as recited in claim1, wherein the display includes a liquid crystal display.
 13. Thedisplay as recited in claim 1, wherein the transistors include thin filmtransistors.
 14. The display as recited in claim 1, further comprisinglogic circuitry for controlling the multiplexing in accordance withcontrol signals.
 15. The display as recited in claim 1, wherein thetransistors are disposed on a substrate and the pixels are formed overthe transistors.
 16. The display as recited in claim 15, wherein thetransistors are disposed on a substrate and the pixels are formed overthe transistors.
 17. An active matrix display comprising: a plurality ofpixels arranged in an array including rows and columns; at least twotrnasistors associated with each pixel, the transistors being seriallyconnected and positioned within the array for switching the pixels onand off; a plurality of data lines running substantially parallel to thecolumns; a plurality of scan lines running substantially parallel to therows; and the data lines and scan lines being coupled to the transistorsof the pixels and shared between the transistors of different pixelssuch that the data lines provide data multiplexing for each pixel andthe scan lines provide gate multiplexing for each pixel by selectivelyenabling the at least two transistors for each pixel in accordance withdata signals on the data lines and gate signals on the gate lines,wherein the data signal multiplexing comprises L:1 multiplexing, and thegate signal multiplexing comprises M:1 multiplexing where L and M eachcomprise an integer greater than one, respectively.
 18. The display asrecited in claim 17, wherein one of the at least two transistors isshared between adjacent pixels.
 19. The display as recited in claim 17,wherein the pixels modulate light in a transmissive mode.
 20. Thedisplay as recited in claim 17, wherein the pixels modulate light in areflective mode.
 21. The display as recited in claim 17, wherein controllines select pixels in different rows simultaneously.
 22. The display asrecited in claim 17, wherein the pixels share a data line.
 23. Thedisplay as recited in claim 17, wherein the pixels each have a differentdata line.
 24. The display as recited in claim 17, wherein the scanlines include capacitance storage lines.
 25. The display as recited inclaim 17, wherein the control lines are coupled to the transistors by alow impedance path.
 26. The display as recited in claim 25, wherein thelow impedance path includes a capacitor.
 27. The display as recited inclaim 17, wherein the display includes a liquid crystal display.
 28. Thedisplay as recited in claim 17, wherein the transistors include thinfilm transistors.
 29. The display as recited in claim 17, furthercomprising logic circuitry for controlling the multiplexing inaccordance with control signals.
 30. The display as recited in claim 17,wherein the array comprises rows and columns and control lines selectthe pixels in different rows simultaneously.
 31. The display as recitedin claim 30, wherein the control lines include data lines and thesimultaneously selected pixels share a data line.
 32. The display asrecited in claim 30, wherein the control lines include data lines andthe simultaneously selected pixels each use a different data line. 33.An active matrix display comprising: a plurality of pixels arranged inan array; at least two transistors associated with each pixel, thetransistors serially connected to each other and disposed within thearray for switching the pixels on and off according to data signals andgate signals; and a data line coupled to a first end of the seriallyconnected transistors and shared between the transistors of differentpixels; a second end of the serially connected transistors coupling to astorage device and the pixel; the serially connected transistorsproviding multiplexing for at least one of data signal multiplexing andgate signal multiplexing of each pixel by selectively enabling the atleast two transistors for each pixel in accordance with the gatesignals, wherein the data signal multiplexing comprises L:1multiplexing, and the gate signal multiplexing comprises M:1multiplexing where L and M each comprise an integer greater than one,respectively.
 34. The display as recited in claim 33, wherein the arraycomprises rows and columns and control lines select the pixels indifferent rows simultaneously.